SR Flip Flops and its types: Active High and Active Low SR Flip Flops

In the domain of digital electronics, a variety of devices orchestrate a symphony of binary operations. Among these, the SR Flip Flop plays an essential role. An SR Flip Flop (Set-Reset Flip Flop) is a type of latch that maintains its output state until a specific input condition is met. The 'set' and 'reset' inputs control this state, making SR Flip Flops an integral component of memory storage units and sequential logic circuits.

Within the realm of SR Flip Flops, two specific types rise to prominence: the Active High SR Flip Flop and the Active Low SR Flip Flop.

• The Active High SR Flip Flop functions such that the outputs (Q and Q') respond when the input signals 'set' (S) and 'reset' (R) are at a high logic level (logic 1). Its Boolean expressions are as follows:
  $Q = S + R'Q'$
  $Q' = R + SQ$

  The aforementioned expressions represent OR and AND operations. In this case, if both 'set' and 'reset' inputs are low (logic 0), the outputs maintain their previous state, performing their primary role of state retention.

• The Active Low SR Flip Flop differs from its counterpart in its response to logic levels. In this case, the flip flop responds when 'set' (S) and 'reset' (R) inputs are at a low logic level (logic 0). The Boolean expressions are similar to those of the Active High SR Flip Flop but involve an inversion at the inputs:
  $Q = S' + RQ'$
  $Q' = R' + SQ$

  The logic operation involves the combination of AND and OR operations, similar to the Active High SR Flip Flop. The role of the Active Low SR Flip Flop is also to maintain its previous state when both inputs are high (logic 1).

Despite their seemingly simple roles, the manipulation of SR Flip Flops' output states forms the basis for various more complex memory storage units and sequential circuits.

As digital technology continues to expand and become more complex, the need for devices like SR Flip Flops, that can retain state and manipulate data, grows. SR Flip Flops can be found in complex systems such as digital registers, counters, and in more advanced components of microprocessors and digital signal processors.

Moreover, understanding the functions of Active High and Active Low SR Flip Flops, their Boolean expressions, and applications can provide profound insights into the world of digital electronics and computer architecture.

Diving Deep into the World of SR Flip Flops

Both Active High and Active Low SR Flip Flops consist of basic building blocks known as logic gates. These gates, like NOR and NAND gates, work in tandem to govern the binary operations of these Flip Flops. An understanding of their functioning is paramount to harnessing their potential and propelling the advancement of digital systems.

Now that we have explored the fundamentals of SR Flip Flops, it is time to apply this knowledge. In the subsequent sections, we will delve into practical activities like the verification of truth tables for Active High and Active Low SR Flip Flops using Proteus software. This powerful tool aids in the simulation of electronic circuits and helps bring our theoretical understanding to life. With a hands-on approach, a deeper understanding of SR Flip Flops can be achieved, highlighting their importance in the realm of digital systems, appealing to a wide range of learners, from novices to seasoned professionals.

Procedures of Doing the Experiment

Active High SR Flip Flop

Title

Implementation of Active High SR Flip Flop Using AND and NOR Gates in Proteus Software

Aim

To implement and validate the operation of an Active High SR Flip Flop using Proteus software simulation with 7408 AND gate IC and 7402 NOR gate IC.

Requirements

Proteus software, 7408 AND gate IC, 7402 NOR gate IC, clock signal generator, Logic State, and Logic Probe tools.

Theory

An Active High SR (Set-Reset) Flip Flop is a basic memory device that can store a single bit of data. It is called "active high" because it reacts to high logic levels. The Flip Flop has two inputs, S (Set) and R (Reset), and two outputs, Q and Q'. When the Set input is high, the Q output becomes high, and when the Reset input is high, the Q' output becomes high. This circuit can be implemented using a combination of AND gates (7408) and NOR gates (7402).

Truth Table of Active High SR Flip Flop

Procedure

1. Open Proteus, create a new schematic capture.
2. Add the 7408 AND gate IC, 7402 NOR gate IC, clock signal generator, Logic State, and Logic Probe (Big) from the pick device menu to the dashboard.
3. Place the AND gates, NOR gates, clock signal generator, Logic State, and Logic Probe tools onto the schematic.
4. Connect the components to form an Active High SR Flip Flop: The S and R inputs connect to one input of the AND gates. The clock signal connects to the second input of the AND gates. The output of each AND gate connects to one input of a NOR gate. The output of each NOR gate connects to the second input of the other NOR gate. The outputs of these NOR gates are Q and Q'.
5. Run the simulation and observe the Q and Q' outputs for all possible input combinations of S, R, and Clock signal.
6. Verify the simulation results against the expected truth table of an Active High SR Flip Flop.

Result

Image Note: Image has a error. NAND Gate instead of AND Gate is used here as simulation fails when AND is used.

The simulation results match the Active High SR Flip Flop operation, validating its correct functionality.

Conclusion

The Active High SR Flip Flop has been successfully implemented and its operation verified using Proteus software, confirming its proper operation as a memory device in digital circuits.

Active-Low SR Flip Flop

Title

Implementation of Active-Low SR Flip Flop Using NAND Gates with Clock Signal in Proteus Software

Aim

To implement and validate the operation of an active-low SR Flip Flop with a clock signal using Proteus software simulation with NAND (7400) gate IC.

Requirements

Proteus software, 7400 NAND gate IC, clock signal generator, Logic State, and Logic Probe tools.

Theory

An active-low SR (Set-Reset) Flip Flop is a basic memory device to store a single bit of data, where the inputs are active when low. This version of SR Flip Flop uses a clock signal. It consists of two inputs, Set (S) and Reset (R), and two outputs, Q and Q' (Q bar). The Flip Flop operates in such a way that the Q output is the inverse of Q' output. Here, we will use the 7400 IC which contains NAND gates. The behavior of the active-low SR Flip Flop can be understood through its truth table.

Truth Table of Active-Low SR Flip Flop

Procedure

1. Open Proteus, create a new schematic capture.
2. Add the 7400 NAND gate IC, Clock Signal generator, Logic State, and Logic Probe (Big) from the pick device menu to the dashboard.
3. Place the NAND gates, Clock Signal generator, Logic State, and Logic Probe tools onto the schematic.
4. Connect the components to form an active-low SR Flip Flop: S and R inputs go to the first input of separate NAND gates (7400), the second input of the NAND gates connect to the Clock Signal, the output of each NAND gate connects to one input of the other two NAND gates, the outputs of these NAND gates are Q and Q'.
5. Run the simulation and observe the Q and Q' outputs for all possible input combinations of Set (S), Reset (R), and Clock signal.
6. Verify the simulation results against the expected truth table of an active-low SR Flip Flop.

Result

The simulation results match the active-low SR Flip Flop operation, validating its correct functionality.

Conclusion

The Active-Low SR Flip Flop has been successfully implemented and its operation verified using Proteus software, confirming its proper operation as a basic memory device in digital circuits.

FAQs

Here are some frequently asked questions about SR Flip Flops and their verification in Proteus.

Challenge Yourself

Take your understanding of SR Flip Flops to the next level by trying these challenges.